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hcpl-m456 small outline, 5 lead intelligent power module optocoupler data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. features performance specified for common ipm applications over industrial temperature range: -40 c to 100 c fast maximum propagation delays t phl = 400 ns, t plh = 550 ns minimized pulse width distortion (pwd = 370 ns) very high common mode rejection (cmr): 15 kv/ s at v cm = 1500 v ctr > 44% at i f = 10 ma safety approval ul recognized per ul1577 (file no. e55361) C 3750vms for 1 minute lead free option -000e applications ipm isolation isolated igbt/mosfet gate drive ac and brushless dc motor drives industrial inverters schematic diagram the connection of a 0.1 f bypass capacitor between pins 4 and 6 is recommended. truth table led v o on l off h description the hcpl-m456 consists of a gaasp led optically coupled to an integrated high gain photo detector. minimized propagation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. specifications and performance plots are given for typical ipm applications. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product 6 5 4 1 3 shield
2 ordering information hcpl-m456 is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount tape & reel iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-m456 -000e no option so-5 x 100 per tube -500e #500 x x 1500 per reel -060e -060 x x 100 per tube -560e -560 x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-m456-560e to order product of so-5 surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: hcpl-m456 to order product of so-5 surface mount package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe. hcpl-m456 outline drawing pin location (for reference only) mxxx xxx 6 5 4 3 1 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) v cc v out gnd cathode anode 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.15 0.025 (0.006 0.001) 0.71 (0.028) min 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches) * maximum mold flash on each side is 0.15 mm (0.006) note: floating lead protrusion is 0.15 mm (6 mils) max. type number (last 3 digits) date code 7 max. max. lead coplanarity = 0.102 (0.004)
3 figure 1. 5 pin soic package (jedec mo-155) device outline drawing. land pattern recommendation absolute maximum ratings parameter symbol min. max. units storage temperature t s -55 125 c operating temperature t a -40 100 c average input current [1] i f(avg) 25 ma peak input current [2] (50% duty cycle, <1 s pulse width) i f(peak) 50 ma peak transient input current (<1 s pulse width, 300 pps) i f(tran) 1.0 a reverse input voltage (pin 3-1) v r 5 volts average output current (pin 5) i o(avg) 15 ma output voltage (pin 5-4) v o -0.5 30 volts supply voltage (pin 6-4) v cc -0.5 30 volts output power dissipation [3] p o 100 mw total power dissipation [4] p t 145 mw infrared and vapor phase reflow temperature see reflow thermal profile below. 8.27 (0.325) 2.0 (0.080) 2.5 (0.10) 1.3 (0.05) 0.64 (0.025) 4.4 (0.17) dimension in millimeters (inches)
4 solder reflow thermal profile recommended pb-free ir profile note: non-halide flux should be used. note: non-halide flux should be used. recommended operating conditions parameter symbol min. max. units power supply voltage v cc 4.5 30 volts output voltage v o 0 30 volts input current (on) i f(on) 10 20 ma input voltage (off) v f(off ) -5 0.8 v operating temperature t a -40 100 c 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering time 200c preheating time 150 c, 90 + 30 sec. 2.5 c 0.5c/sec. 3 c + 1 c/C0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/C0.5c/sec. reflow heating rate 2.5 c 0.5c/sec. 217 c ramp-down 6c/sec. max. ramp-up 3c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c
5 regulatory notes the hcpl-m456 is recognized under the component program of u.l. (file no. 55361) for dielectric withstand proof voltages of 2500 v rms , 1 minute. insulation related specifications parameter symbol value units conditions minimum external air gap external clearance l(101) 5 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking external creepage l(102) 5 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap internal clearance 0.08 mm insulation thickness between emitter and detector; also known as distance through insulation. tracking resistance cti 200 volts din iec 112/vde 0303 part 1 isolation group iiia material group din vde 0110 electrical specifications over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off ) = -5 v to 0.8 v parameter symbol min. typ.* max. units test conditions fig. note current transfer ratio ctr 44 90 % i f = 10 ma, v o = 0.6 v 5 low level output current i ol 4.4 9.0 ma i f = 10 ma, v o = 0.6 v 2,3 low level output voltage v ol 0.3 0.6 v i o = 2.4 ma input threshold current i th 1.5 5.0 ma v o = 0.8 v, i o = 0.75 ma 2 9 high level output current i oh 550 av f = 0.8 v 4 high level supply current i cch 0.6 1.3 ma v f = 0.8 v, v o = open 9 low level supply current i ccl 0.6 1.3 ma i f = 10 ma, v o = open 9 input forward voltage v f 1.5 1.8 v i f = 10 ma 5 temperature coefficient of forward voltage v f / t a -1.6 mv/c i f = 10 ma input reverse breakdown voltage bv r 5vi r = 10 a input capacitance c in 60 pf f = 1 mhz, v f = 0 v input-output insulation voltage v iso 3750 v rms rh < 50%, t = 1 min, t a = 25 c 6, 7 resistance (input - output) r i-o 10 12 v i-o = 500 vdc 6 capacitance (input - output) c i-o 0.6 pf f = 1 mhz 6 *all typical values at 25 c, v cc = 15 v.
6 switching specifications (r l = 20 k ) over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off ) = -5 v to 0.8 v parameter symbol min. typ.* max. units test conditions fig. note propagation delay time to low output level t phl 30 200 400 ns c l = 100 pf i f(on) = 10 ma, v f(off ) = 0.8 v, v cc = 15.0 v, v thlh = 2.0 v, v thhl = 1.5 v 6, 8-12 8, 9 100 ns c l = 10 pf propagation delay time to high output level t plh 270 400 550 ns c l = 100 pf 130 c l = 10 pf pulse width distortion pwd 200 450 ns c l = 100 pf 13 propagation delay difference between any 2 parts t plh -t phl -150 200 450 ns 10 output high level common mode transient immunity |cm h | 15 30 kv/ si f = 0 ma, v o > 3.0 v v cc = 15.0 v, c l = 100 pf, v cm = 1500 v p-p , t a = 25 c 711 output low level common mode transient immunity |cm l |1530 kv/ si f = 10 ma, v o < 1.0 v 12 *all typical values at 25 c, v cc = 15 v. notes: 1. derate linearly above 90 c free-air temperature at a rate of 0.8 ma/c. 2. derate linearly above 90 c free-air temperature at a rate of 1.6 ma/c. 3. derate linearly above 90 c free-air temperature at a rate of 3.0 mw/c. 4. derate linearly above 90 c free-air temperature at a rate of 4.2 mw/c. 5. current transfer ratio in per cent is defined as the ratio of output collector current (i o ) to the forward led input current (i f ) times 100. 6. device considered a two-terminal device: pins 1 and 3 shorted together and pins 4, 5 and 6 shorted together. 7. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o 5 a). 8. pulse: f = 20 khz, duty cycle = 10%. 9. use of a 0.1 f bypass capacitor connected between pins 4 and 6 can improve performance by filtering power supply line noise. 10. the difference between t plh and t phl between any two parts under the same test condition. (see ipm dead time and propagation delay specifications section.) 11. common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). 12. common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 13. pulse width distortion (pwd) is defined as |t phl - t plh | for any given device.
7 led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of opto- coupler cmr failure is capacitive coupling from the input side of the opto coupler, through the package, to the detector ic as shown in figure 14. the hcpl-m456 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and the opto coupler output pin and output ground as shown in figure 15. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocou- pler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or off ) during common mode transients. for example, the recommended application circuit (figure 13), can achieve 15 kv/ s cmr while minimizing component complexity. note that a cmos gate is recommended in figure 13 to keep the led off when the gate is in the high state. another cause of cmr failure for a shielded optocoupler is direct coupling to the optocoupler output pins through c ledo1 in figure 15. many factors influence the effect and magni tude of the direct coupling including: the position of the led current setting resistor and the value of the capacitor at the optocoupler output (c l ). techniques to keep the led in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. cmr with the led on (cmrl) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriv- ing the led current beyond the input threshold so that it is not pulled below the threshold during a transient. the recommended minimum led current of 10 ma provides adequate margin over the maximum i th of 4.0 ma (see figure 2) to achieve 15 kv/ s cmr. the placement of the led current setting resistor effects the ability of the drive circuit to keep the led on during transients and interacts with the direct coupling to the optocoupler output. for example, the led resistor in figure 16 is connected to the anode. figure 17 shows the ac equivalent circuit for figure 16 during common mode transients. during a +dv cm /dt in figure 17, the current available at the led anode (itotal) is limited by the series resistor. the led current (i f ) is reduced from its dc value by an amount equal to the current that flows through c ledp and c ledo1 . the situation is made worse because the current through c ledo1 has the effect of trying to pull the output high (toward a cmr failure) at the same time the led current is being reduced. for this reason, the rec- ommended led drive circuit (figure 13) places the current setting resistor in series with the led cathode. figure 18 is the ac equivalent circuit for figure 13 during common mode transients. in this case, the led current is not reduced during a +dv cm /dt transient because the current flowing through the package capacitance is supplied by the power supply. during a -dv cm /dt transient, however, the led current is reduced by the amount of current flowing through c ledn . but, better cmr performance is achieved since the current flowing in c ledo1 during a negative transient acts to keep the output low.
8 ipm dead time and propagation delay specifications the hcpl-m456 includes a propagation delay difference specification intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 22) are off. any overlap in q1 and q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. to minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the ipm igbt gate drive circuit. considering only the delay characteristics of the optocoupler (the charac ter is tics of the ipm igbt gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn-on (t phl ) and turn-off (t plh ) propagation delay specifications, preferably over the desired operating temperature range. the limiting case of zero dead time occurs when the input to q1 turns off at the same time that the input to q2 turns on. this case determines the minimum delay between led1 turn-off and led2 turn-on, which is related to the worst case optocoupler propaga tion delay waveforms, as shown in figure 23. a minimum dead time of zero is achieved in figure 23 when the signal to turn on led2 is delayed by (t plh max - t phl min ) from the led1 turn off. note that the propagation delays used to calculate pdd are taken at equal temperatures since the optocoup lers under consideration are typically mounted in close prox- im ity to each other. (specifically, t plh max and t phl min in the previous equation are not the same as the t plh max and t phl min , over the full operating tempera ture range, specified in the data sheet.) this delay is the maximum value for the propagation delay differ ence specification which is specified at 370 ns for the hcpl-m456 over an operating tempera ture range of -40 c to 100 c. delaying the led signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest t plh and another with the slowest t phl are in the same inverter leg. the maximum dead time in this case becomes the sum of the spread in the t plh and t phl propagation delays as shown in figure 24. the maximum dead time is also equiv alent to the difference between the maximum and minimum propagation delay differ- ence specifications. the maximum dead time (due to the optocoup lers) for the hcpl-m456 is 520 ns (= 370 ns - (-150 ns)) over an operating t emperature range of -40 c to 100 c. cmr with the led off (cmrh) a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a +dv cm /dt transient in figure 18, the current flowing through c ledn is supplied by the parallel combi- nation of the led and series resistor. as long as the voltage developed across the resistor is less than v f(off) the led will remain off and no common mode failure will occur. even if the led momentarily turns on, the 100 pf capacitor from pins 5-4 will keep the output from dipping below the threshold. the recommended led drive circuit (figure 13) provides about 10 v of margin between the lowest opto- coupler output voltage and a 3 v ipm threshold during a 15 kv/ s transient with v cm = 1500 v. additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connec tion in figure 18, to clamp the voltage across the led below v f(off) . since the open collector drive circuit, shown in figure 19, cannot keep the led off during a +dv cm /dt transient, it is not desirable for applications requir ing ultra high cmr h performance. figure 20 is the ac equivalent circuit for figure 19 during common mode transients. essen tially all the current flowing through c ledn during a +dv cm /dt transient must be supplied by the led. cmr h failures can occur at dv/dt rates where the current through the led and c ledn exceeds the input threshold. figure 21 is an alternative drive circuit which does achieve ultra high cmr performance by shunting the led in the off state.
9 normalized output current t a C temperature C c 0.95 0.90 0.85 i f = 10 ma v o = 0.6 v 1.00 0 40 60 100 -40 -20 20 80 1.05 0.80 i oh C high level output current C a t a C temperature C c 1.5 1.0 0.5 2.0 0 40 60 100 -40 -20 20 80 0 4.5 v 30 v v f = 0.8 v v cc = v o = 4.5 v or 30 v i f C forward current C ma 0.001 v f C forward voltage C volts 10 1.0 0.1 1000 1.10 1.60 1.20 1.30 1.40 1.50 t a = 25 c 0.01 100 i o C output current C ma 0 i f C forward current C ma 6 4 2 10 8 5101520 0 v o = 0.6 v 100 c 25 c -40 c i f v f + C figure 2. typical transfer characteristics. figure 3. normalized output current vs. temperature. figure 4. high level output current vs. temperatur e. figure 5. input current vs. forward voltage.
10 figure 7. cmr test circuit. figure 6. propagation delay test circuit. typical cmr waveform. 0.1 f v cc = 15 v 20 k 6 5 4 1 3 shield i f(on) =10 ma v out c l * + C *total load capacitance + C i f v o v thhl t phl t plh t f t r 90% 10% 90% 10% v thlh 0.1 f v cc = 15 v 20 k 6 5 4 1 3 shield a i f v out 100 pf* + C *100 pf total capacitance + C + C b v ff v cm = 1500 v v cm dt o v v o v o switch at a: i f = 0 ma switch at b: i f = 10 ma v cc v ol v cm t v t =
11 figure 8. propagation delay with external 20 k rl vs. temperature. figure 9. propagation delay vs. load resistance. figure 10. propagation delay vs. load capacitance. figure 12. propagation delay vs. input current. figure 11. propagation delay vs. supply voltage. t p C propagation delay C ns t a C temperature C c 400 300 200 500 0 40 60 100 -40 -20 20 80 100 t p C propagation delay C ns 0 c l C load capacitance C pf 800 600 400 1400 200 1000 1200 100 200 300 400 0 500 t p C propagation delay C ns 0 v cc C supply voltage C v 800 600 400 1400 200 1000 10 15 20 25 530 1200 t p C propagation delay C ns 100 i f C forward led current C ma 300 500 200 400 10 15 5 020 t plh t phl t plh t phl i f = 10 ma v cc = 15 v c l = 100 pf r l = 20 k (external) i f = 10 ma v cc = 15 v c l = 100 pf t a = 25 c t p C propagation delay C ns r l C load resistance C k 600 400 200 800 30 50 010 20 40 t plh t phl t plh t phl i f = 10 ma v cc = 15 v r l = 20 k t a = 25 c i f = 10 ma c l = 100 pf r l = 20 k t a = 25 c t plh t phl v cc = 15 v c l = 100 pf r l = 20 k t a = 25 c
12 figure 14. optocoupler input to output capacitance model for unshielded optocouplers. figure 13. recommended led drive circuit. figure 15. optocoupler input to output capacitance model for shielded optocouplers. figure 16. led drive circuit with resistor connected to led anode (not recommended). figure 17. ac equivalent circuit for figure 16 during common mode transients. figure 18. ac equivalent circuit for figure 13 dur ing common mode transients. 0.1 f v cc = 15 v 20 k 6 5 4 1 3 shield cmos 310 +5 v v out 100 pf + C *100 pf total capacitance 6 5 4 1 3 c ledp c ledn 6 5 4 1 3 c ledp c ledn shield c led01 0.1 f v cc = 15 v 20 k 6 5 4 1 3 shield cmos 310 +5 v v out 100 pf + C *100 pf total capacitance 20 k 6 5 4 1 3 * the arrows indicate the direction of current flow for +dv cm /dt transients. 300 v out 100 pf i cledp c ledn shield c led01 + C i total * i cled01 i f v cm 20 k 6 5 4 1 3 * the arrows indicate the direction of current flow for +dv cm /dt transients. ** optional clamping diode for improved cmh performance. v r < v f (off) during +dv cm /dt. v out 100 pf c ledp c ledn shield c led01 + C i cledn * 300 + v r ** C v cm
13 figure 21. recommended led drive circuit for ultra high cmr. figure 19. not recommended open collector led drive circuit. f igure 20. ac equivalent circuit for figure 19 during common mode t ransients. figure 22. typical application circuit. 6 5 4 1 3 shield q1 +5 v 20 k 6 5 4 1 3 * the arrows indicate the direction of current flow for +dv cm /dt transients. v out 100 pf c ledp c ledn shield c led01 + C i cledn * q1 v cm 6 5 4 1 3 shield +5 v 0.1 f 20 k 6 5 4 1 3 shield cmos 310 +5 v v out1 hcpl-m456 i led1 v cc1 0.1 f 20 k 6 5 4 1 3 shield cmos 310 +5 v v out2 hcpl-m456 i led2 v cc2 m q2 q1 -hv +hv ipm hcpl-m456 hcpl-4506 hcpl-m456 hcpl-m456 hcpl-m456
figure 23. minimum led skew for zero dead time. figure 24. waveforms for deadtime calculation. v out1 v out2 i led2 t plh max. pdd* max. = (t plh - t phl ) max. = t plh max. - t phl min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference note: the propagation delays used to calculate pdd are taken at equal temperatures. v out1 v out2 i led2 t plh min. maximum dead time (due to optocoupler) = (t plh max. - t plh min. ) + (t phl max. - t phl min. ) = (t plh max. - t phl min. ) - (t plh min. - t phl max. ) = pdd* max. - pdd* min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference t plh max. t phl max. pdd* max. max. dead time note: the propagation delays used to calculate the maximum dead time are taken at equal temperatures. for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. av02-3306en - december 14, 2011

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